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Designing with UltraScale Memory IP
Learn how to create an UltraScale memory interface design using the Vivado Memory Interface Generator (MIG). This video will show you how to configure a MIG IP core for UltraScale Devices, including I/O Bank planning for the MIG IP I/Os. An example design is created and implemented for validation. The process for modifying specific I/O pin locations is also demonstrated. For More Vivado Tutorials please visit: 2015-05-12 오전 9:21:41